The present invention relates to an autozeroed comparator suitably adapted for high-speed sampling.
In a conventional parallel comparing A/D converter, a number of comparators for discriminating quantization levels are arranged in parallel with each other. The comparators simultaneously compare the input signals, and the converter produces a suitable code in accordance with outputs from these comparators. In an A/D converter of this type, each comparator comprises a differential amplifier such as an operational amplifier. However, if such operational amplifiers are used, errors are caused by an offset voltage and an offset current.
In view of this problem, a high-speed and high-precision autozeroed comparator as shown in FIG. 1 exists, which can, theoretically, avoid offset error. In a comparator of this type, a reference voltage Vref is supplied to a first input terminal 1, and an input signal Vin to be compared therewith is supplied to a second input terminal 2. The first and second input terminals 1 and 2 are controlled by a clock signal .phi. and an inverted signal .phi. thereof, respectively. For this purpose, the first and second input terminals 1 and 2 are connected in parallel with each other through first and second switches 3 and 4 each comprising an FET analog switch and are then connected to one terminal of a capacitor 5. The other terminal of the capacitor 5 is connected to the input terminal of an inverting amplifier 6. A third switch 7 is arranged between the input and output terminals of the inverting amplifier 6 and is controlled by the clock signal .phi.. The output terminal of the inverting amplifier 6 is connected to an output terminal 8.
With the comparator as described above, as indicated by the timing charts in FIG. 2, during the "H" (high) level of the clock signal .phi. ((a) in FIG. 2), the first and third switches 3 and 7 are turned on and the second switch 2 is turned off to short-circuit the input and output terminals of the inverting amplifier 6. In this manner, a voltage between the input and output terminals of the inverting amplifier 6 reaches a threshold voltage Vthr, that is, an operating voltage as a reference of operation. In the input/output characteristic curve (input voltage Vin versus output voltage Vout) of the inverter as shown in FIG. 3, the operating voltage corresponds to a voltage V0 at which the input and output voltages are equal to each other (Vin=Vout). At this time, the reference voltage Vref is applied to the input side of the capacitor 5. During the "H" level of the clock signal .phi. ((b) in FIG. 2), the first and third switches 3 and 7 are turned off and the second switch 4 is turned on. Thus, the input signal Vin is supplied to the input side of the capacitor 5. Accordingly, the input voltage to the inverting amplifier 6 changes from the threshold voltage Vthr to the voltage difference between the reference voltage Vref and the input signal Vin.
If it is assumed that the inverting amplifier 6 has a high input impedance and the capacitor 5 does not leak any charge, the capacitor 5 will store a constant amount of charge. When the potential at the input side of the capacitor 5 changes from Vref to Vin, the potential at the output side thereof changes from the threshold voltage Vthr to Vthr+(Vref-Vin). Such a change in the input voltage to the inverting amplifier 6 can be produced from the output terminal 8 after being multiplied by the gain of the inverting amplifier 6.
A plurality of comparators each having the configuration described above are arranged; an input voltage is commonly supplied to one input terminal of each of the comparators while voltages weighted by different weighting coefficients are supplied to the other input terminal of each of the comparators. A comparison output from each comparator is supplied to a decoder for decoding. Then, an analog-to-digital converter (to be referred to as an A/DC hereinafter) is obtained which converts an analog value supplied as an input signal to a digital signal.
When a video signal having a frequency of about 3.58 MHz is to be converted to a digital signal using such an A/DC, the sampling frequency must be at least two times and preferably four times, i.e., 15 MHz, the original frequency so as to provide a practically acceptable conversion precision, from the known sampling theorem.
When a comparator, the most important part of the A/DC, has the circuit configuration as shown in FIG. 1 and a general bulk CMOS element is used, a required conversion speed cannot be obtained. When a comparator having the circuit configuration as shown in FIG. 1 is integrated by the currently available micropatterning technique, the maximum conversion speed attainable is about 10 MHz samples per second.
If the rate of change over time of the gain of an amplifying means of such an A/DC is given as a, supply of a voltage difference Va-Vb between input voltages Va and Vb to the input terminals produces an output voltage of (Va-Vb).times.a.times.t where t is time from the start of amplifying operation. Meanwhile, the rate of change a of the gain of such an amplifying means decreases over time. When a product a.multidot.t of the rate of change a and time t reaches saturation at a certain time point, the output voltage remains constant thereafter.
In an amplifying means used in an A/DC for digital conversion of a signal having a high frequency such as a video signal, the amplifying time is as short as 10 ns to 100 ns. For this reason, the sampling period of the amplifying means ends before the output reaches saturation level. When the sampling period is short, as in this case, the gain of the amplifying means can be considered to be substantially proportional to the amplifying period. Thus, when the amplifying period is doubled, the effective gain is substantially doubled. However, when the amplifying period is doubled, the sampling frequency is rendered substantially half the original frequency and conversion speed is also reduced to substantially half the original speed. This means that digital conversion of a signal having a high frequency such as a video signal cannot be performed with high precision.
A comparator also exists with the circuit configuration shown in FIG. 1 using a CMOS element of SOS (silicon on sapphire) structure and which can perform high-speed conversion of 20 MHz samples per second. However, such a comparator results in high cost in both the manufacture process and materials and cannot be used in cases where cost is of prime importance.